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A.1.14 BSEL# (I/O)
The BSEL# (Bus Select) signal is used for future
Slot 1 processors and motherboards. This signal
must be tied to GND for proper processor operation.

A.1.20 EMI
EMI pins should be connected to motherboard
ground and/or to chassis ground through zero ohm
(0 ) resistors. The zero ohm resistors should be
placed in close proximity to the Slot 1 connector. The
path to chassis ground should be short in length and
have a low impedance.

A.1.41 SLOTOCC# (O)
The SLOTOCC# signal is defined to allow a system
design to detect the presence of a terminator card or
processor in a Pentium II connector. Combined with
the VID combination of VID[4:0] = 11111 (see
Section 2.6.), a system can determine if a Pentium II
connector is occupied, and whether a processor core
is present. See Table 32 for states and values for
determining the type of package in the Slot 1
connector.

A.1.42 SLP# (I)
The SLP# (Sleep) signal, when asserted in Stop
Grant state, causes processors to enter the Sleep

state. During Sleep state, the processor stops
providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or
interrupts. The processor will recognize only
assertions of the SLP#, STPCLK#, and RESET#
signals while in Sleep state. If SLP# is deasserted,
the processor exits Sleep state and returns to Stop
Grant state, restarting its internal clock signals to the
bus and APIC processor core units.

A.1.16. BR0#(I/O), BR[3:1]# (I)
The BR[3:0]# pins are the physical bus request pins that drive the BREQ[3:0]# signals in the
system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor
pins. #. Table A-4 gives the rotating interconnect between the processor and bus signals.

CPUPRES# is a ground pin defined to allow a designer to detect the presence of a processor in a socket.

11.4.3. Phase Lock Loop (PLL) Decoupling
Isolated analog decoupling is required for the internal PLL. This should be equivalent to 0.1µF
of ceramic capacitance. The capacitor should be type Y5R or better and should be across the
PLL1 and PLL2 pins of the Pentium Pro processor. (“Y5R” implies 15% tolerance over the
temperature range -30C to +85C.)

11.11. UNUSED PINS
All RESERVED pins must remain unconnected. All pins named TESTHI must be pulled up, no
higher than VccP, and may be tied directly to VccP. All pins named TESTLO pulled low and
may be tied directly to Vss.

17.3.2. Upgrade Present Signal (UP#)
The Upgrade Present signal is used to prevent operation of voltage regulators providing a potentially
harmful voltage to the OverDrive processor, and to prevent contention between on-board
regulation and the OverDrive VRM. UP# is an open collector output, held high using a pull-up
resistor on the motherboard tied to +5 Volts.

2.12. GTL+ System Bus
Specifications
It is recommended to have the GTL+ bus routed in a
daisy-chain fashion with termination resistors at each
end of every signal trace. These termination resistors
are placed electrically between the ends of the signal
traces and the VTT voltage supply and generally are
chosen to approximate the substrate impedance. The
valid high and low levels are determined by the input
buffers using a reference voltage called VREF.
Table 9 lists the nominal specification for the GTL+
termination voltage (VTT). The GTL+ reference
voltage (VREF) should be set to 2/3 VTT for the core
logic using a voltage divider on the motherboard. It is
important that the motherboard impedance be
specified and held to a ±20% tolerance, and that the
intrinsic trace capacitance for the GTL+ signal group
traces is known. For more details on GTL+, see the
Pentium® II Processor Developer’s Manual (Order
Number 243341) and the Pentium® II Processor
GTL+ Guidelines (Order Number 243330).