MR BIOS PostCode

если вдруг кому-то пригодится.... Нигде в инете не нашел, почему кладу здесь.

Post Code for MR BIOS

Diagnostic Port 80H Post Codes

00/00H Cold Boot commences (Not seen with warm boot)
01/00H HOOK 00 OEM specific typically resets chipset to defult
02/02H Disable critical 1/0: 6845s, 8237s, 765, and parity latches.
03/03H BIOS checksum test
04/04H Page register test (Ports 81-8f)
05/05H 8042(Keyboard Controller) Selftest
06/06H Gang Port Init: 8237 m/s, 8254 ch2/1 RTC REG F/A, 8259m/s
07/07H HOOK 01. OEM specific typically disables cache, shadow.
08/08H Refresh toggle test(PORTB)
09/09H Pattern test master/slave 8259 mask regs.
10/0AH Base 64k memory test.
11/0BH Pattern test master/slave 8259 mask regs.
12/0CH 8259/IRQ tests, purge powerup ints
13/0DH 8254 channel-0 test and initialization
14/0EH 8254 channel-2 toggle test, test speaker circuitry

15/0FH RTC tests/inits:REG-B, write/readback NVRAM, PIE test
19/13H Hook 02 OEM specific select 8MHz bus.
16/10H Video initialization
17/11H CMOS checksum test
18/12H Signon msg Accept KB BAT perform 1st try KB int, cold boot delay
20/14H Size/Test base memory (low 64K already done)
21/15H Perform 2nd try KB int if necessary
22/16H HOOK 03 OEM specific Size/Test cache
23/17H Test A20 gate off then on.
24/18H Size/Test extended memory
25/19H HOOK 04 and Size/Test system memory("special"OEM memory)
26/1AH Test RTC update in progress and validate time
27/1BH Serial port determination off board/on board
28/1CH Parallel port determination off board/on board
29/1DH Coprocessor determination/initialization
30/1EH Floppy controller test/determination, CMOS validation
31/1FH Fixed disk controller test/determination CMOS validation
32/20H Rigorous CMOS parameter validation display other config changes
33/21H Front Panel lock check wiat for user to acknowledge errors
34/22H Set numlock password security trap dispatch to setup utility
35/23H HOOK 05 OEM specific 36/24H Set typematic rate
40/28H HOOK 06, OEM specific typically enables shadow cache turbo
37/25H Floppy subsystem initialization 38/26H Fixed subsystems initialization
39/27H ACK errors set primary adapter video mode
41/29H Disable A20 gate set low stack install C800 E000 ROMs
42/2AH ACK errors set video mode set DOS time variables from RTC
43/2BH Disable A20 gate set low stack install C800 E000 ROMs
44/2CH Install E000 ROM
45/2DH ACK errors
46/2EH HOOK 07 OEM specific Log in EMS (if built in)
47/2FH Pass control to INT 19(boot disk)

Если данная информация оказалась полезной/интересной - плюсаните, пожалуйста:

Аватар пользователя icbook

Root писал(-а):
если вдруг кому-то пригодится.... Нигде в инете не нашел, почему кладу здесь.

Сие касается довольно-таки пожилого MrBIOS v3.3.

Аватар пользователя Baza

А вот АБИТ АВАРД БИОС ерр.коде:)

cf - test cmos r/w functionality
co - early chipset initialization:
-disable shadow ram
-disable l2 cache socket 7 and down
-program basic chipset registers
c1 - detect memory
-auto detection of DRAM size , type , ecc
-auto detection of cache(socket 7 and down)
c3 - expand compressed BIOS code to DRAM
c5 - call chipset hook to copy BIOS back to E000 and F000 shadow RAM
01 - expand the Xgroup codes locating in physical address 1000:0
03 - initial Superio_early_Init switch
05 - 1. Blank out screen
2. clear CMOS error flag
07 - 1.clear 8042 interface
2.initialize 8042 self-test
08 - 1.test special keyboard controller for winbond 977 series Super I/O chips
2.enable keyboard interface
0A - 1.disable ps/2 mouse interface (optional) detect ports for keyboard and mouse followed by a port and interface swap (optional)
3.reset keyboard for winbond 977 series Super I/O chips
0E - test F000h segment shadow to see whether it is R/W-able or not. if test fails, keep beeping the speaker
10 - auto detect flash type to load appropriate flash R/W codes into the runtime area in F000 for ESCD & DMI support
12 - Use walking 1's algorithm to check out interface in CMOS circuitry. Also set realtime clock power status , and then check for override
14 - program chipset default values into chipset. Chipset default values are MODBINable by OEM customers
16 - initial onboard clock generator if Early_Init_Onboard_Generator is defined. see also post 26
18 - detect cpu information including brand, SMI type(cyrix or intel) and cpu level(586 or 686)
1B - initial interrupts vector table. if no special specified, all H/W interrupts are directed to SPURIOUS_soft_HDLR
1D - initial EARLY_PM_INIT switch
1F - load keyboard matrix (notebook platform)
21 - HPM initialization (notebook platform )
23 - 1.check validity of RTC value
2.load CMOS setting into BIOS stack . if CMOS checksum fails use default value instead
24 - prepare bios resource map for pci and pnp use.
25 - early pci initialization:
-enumerat pci bus number
-assign memory and I/O resource
-search for a valid vga device and vga bios , and put it into C000:0
26 - 1.if early INIT_ONBOARD_GENERATOR is not defined onboard clock generator initialization.Disable respective clock resource to empty pci and dimm slots
2.init onboard PWM
3.init onboard H/W monitor devices
27 - initialize INT 09 buffer
29 - 1.program cpu internal MTRR(p6 and pII) for 0-640k memory address
2.initialize the APIC for pentium class cpu
3.program early chipset according to cmos setup
4.measure cpu speed
2B - invoke video bios
2D - 1.initialize double-byte language font(optional)
2.put information on screen display, including award title, cpu type , cpu speed , full screen logo
33 - reset keyboard if Early_Reset_KB is defined
35 - test DMA channel 0
37 - test DMA channel 1

39 - test DMA page registers
3C - test 8254
3E - test 8259 interrupt masked bits for channel 1
40 - test 8259 interrupt masked bits for channel 2
43 - test 8259 functionality
47 - initialize eisa slot
49 - 1.calculate total memory by testing the last double word of each 64k page
2.program writes allocation for amd k5 cpu
4E - 1.program MTRR of M1 cpu
2.initialize l2 cache for p6 class cpu & program cpu with proper cacheable range
3.initialize the APIC for p6 class cpu
4.on mp platform adjust the cacheable range to smaller one in case the cacheable ranges between the cpus are not identical
50 - initialize USB
52 - test all memory (clear all extended memory to 0)
53 - clear password according to H/W jumper (optional)
55 - display number of processors (multi processor platform)
57 - disply PnP logo
early ISA PnP initialization
- assign CSN to every ISA PNP device
59 - initialize the combined Trend Anti-virus code
5B - (optional feature)show message for entering AWDFLASDH.EXE from FDD (optional)
5D - 1. initialize Init_onboard_Super_IO
2. initialize Init_Onboard_AUDIO
60 - okay to enter setup utility
63 - reset keyboard if Early_reset_KB is not defined
65 - initialize PS/2 mouse
67 - prepare memory size information for function call :INT 15h ax=E820H
69 - turn on L2 cache
6B - program chipset registers according to items described in setup & auto-configuration table
6D - 1.assign resources to all PnP devices assign ports to onboard COM if the corresponding item in setup is set to"auto"
6F - 1.initialize floppy controller
2.set up floppy related fields in 40:hardware
75 - detect and install co-processor
76 - (optional feature) enter AWDFLASH.EXE if ;
-AWDFLASH.EXE is found in floppy drive
-ALT+F2 is pressed
77 - detect serial ports & parallel ports
7A - detect and install co-processor
7C - init HDD write protect
7F - switch back to text mode if full screen logo is supported
-if error occurs report errors and wait for keys
-if no errors occur or F1 key is pressed to continue:clear epa or custimization logog
82 - chipset powermanagment hooks
2.recover the text font used by EPA logo(not full screen logo)
3.if password is set , ask for password
83 - save all data in stack back to cmos
84 - initialize ISA PnP boot devices
85 - 1.usb final initialization
2.switch screen back to text mode
87 - NET PC:build SYSID structure
89 - 1.assign IRQ's to PCI devices
2.set up ACPI table at top of memory
8B - 1.invoke all ISAadapter ROM's
2.invoke all PCI ROM's except VGA
8D - 1.enable/disable parity check according to CMOS setup
2.APM initialization
8F - clear noise of IRQ's
93 - read HDD boot sector information for Tren Anti-virus code
94 - 1.enable L2 cache
2.program daylight savings time
3.program boot up speed
4.chipset final initialization
5.power management final initialization
6.clear screen and disable summary table
7.program K6 write allocation
8.program P6 class write combining
95 - update keyboard LED & typematic rate
96 - MP table and upate ESCD
3.set CMOS century to 20h or 19h
4.load CMOS time into DOS timer clock MSIRQ routing table
FF - boot attempt (INT19h)

And more:
8.1. - start power on sequence
8.2. - enable atx power supply
8.3. - atx power supply ready
8.4. - DDR voltage ready
8.5. - setup PWM for CPU core voltage
8.6. - assert PWM for CPU core voltage
8.7. - check CPU core voltage
8.8. - CPU core voltage ready
8.9. - initial clock generator IC
8.A. - north bridge chipset voltage ready
8.B. - AGP voltage ready
8.C. - 3VDUAL voltage ready
8.D. - VDDA 2.5V voltage ready
8.D. - GMCHVTT voltage ready
8.E. - check CPU fan speed
8.F. - assert all power ready
9.0. - complete Uguru initial process
Award bios taking over booting job
9.1. - start power off sequence
9.2. - De-Assert all power
9.3. - Se-Assert power on
9.4. - De-Assert LDT bus power
9.5. - De-Assert PWM for CPU core voltage
9.6. - De-Assert CPU core voltage
9.7. - check CPU core voltage
9.8. - De-Assert ATX power supply
9.9. - complete power off sequence
F.0. - button reset
F.1. - SoftMenu reset
F.2. - power on sequence timeout
F.3. - power off sequence timeout

Добавлено спустя 1 минуту:

может вынести отдельной темой пост коды?

Либо нечему гореть, либо нечем поджечь!

Ленты новостей